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V 的代码
countupdown.v
module countupdown(clk,count,up_down);
input clk,up_down;
output[0:3]count;
reg[0:3]count;
initial count='d5;
always@(posedge clk)begin
if(up_down)begin
count=count+1;
if(count>12)co
tb_bcdcount60.v
module tb_BCDcount60;
reg load,cin,clk,reset;
reg [7:0] data;
wire [7:0] qout;
wire cout;
always #1 clk=~clk;
BCDcount60 c1(.qout(qout),.cout(cout),.data(data),.load
counta3d5_tb.v
module counta3d5_tb;
reg rst,clk,up,dn;
reg [7:0]din;
wire[7:0]dout;
wire par,carry,borrow;
initial din=8'b11010011;
always #1 clk=~clk;
initial begin
clk=0;
global_var.v
module Global_Var;
reg[0:7] RamQ[0:63];
integer index;
reg CheckBit;
initial
begin
for (index=0;index
lfsr_updown_tb.v
`define WIDTH 8
module lfsr_updown_tb();
reg clk;
reg reset;
reg enable;
reg up_down;
wire [`WIDTH-1:0]count;
wire overflow;
initial begin
$monitor("rst%b en%b updown%b cnt%b overflow%b
countu3d5_tb.v
module countu3d5_tb;
reg rst,clk,up,dn;
reg [7:0]din;
wire[7:0]dout;
wire par,carry,borrow;
initial din=8'b11010011;
always #1 clk=~clk;
initial begin
clk=0;
rever_clk.v
module rever_clk(clk,clk_out);
input clk;
output clk_out;
xor u1(clk_out,clk,1'b1);
endmodule
`timescale 1ns/1ns
module rever_clk_tb;
reg clk;
wire clk_out;
always #1 clk=~cl
adder4.v
module adder4(cout,sum,ina,inb,cin);
output [3:0] sum;
output cout;
input [3:0] ina,inb;
input cin;
assign{cout,sum}=ina+inb+cin;
endmodule
`timescale 1ns/1ns
module tb_adder4;
reg
parity_check.v
module Parity_Check;
reg [0:7] a;
reg s;
initial begin
a=8'b11000111;
end
function Parity;
input [0:7] Set;
//output Parity;
//reg Parity;
reg[0:2] Ret;
integer j;
begi
machine.v
module machine(clk,reset,in,out);
input clk,reset,in;
output out;
reg out;
parameter set0=0,hold=1,set1=2;
reg [1:0] state;
always@(posedge clk or negedge reset)
begin
if