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找到约 7,641 项符合
V 的代码
wave.v
module wave(clk,reset,clk1);
input clk,reset;
output clk1;
reg clk1;
reg [1:0]i;
always@(posedge clk or negedge reset)
if(!reset)begin
clk1
counta3d5.v
module counta3d5(rst,clk,up,dn,din,dout,par,carry,borrow);
input rst,clk,up,dn;
input[7:0]din;
output[7:0]dout;
output par,carry,borrow;
reg [7:0]dout;
bin2bcd.v
//
//
//-----------------------------------------------------------------------------------
// DESCRIPTION : Bin to Bcd converter
// Input (data_in) width : 4
//
multiply_tb.v
module Multiply_tb;
reg [7:0]Mplr,Mcnd;
reg Clock,Reset;
wire Done;
wire[15:0]Acc;
always #5 Clock=~Clock;
initial begin
Clock=0;
Reset=1;
#30 Reset=0;
//Mplr=8'b11010011;
//Mcnd=8'
three_divider.v
module three_divider(clk,reset,clk_out);
input clk,reset;
output clk_out;
reg[1:0]i,j;
reg clk1,clk2;
assign clk_out=clk1|clk2;
always@(posedge clk or negedge reset)
if(!reset)begin
clk1
dividern_5.v
//-----------------------------------------------------------
// file name: N-5 divider
// author: Yilong.you
// date: October 14,2008
//----------------------------------------------------
multiply.v
module Multiply(Mplr,Mcnd,Clock,Reset,Done,Acc);//用有限状态机实现乘法
input [7:0]Mplr,Mcnd;
input Clock,Reset;
output Done;
output[15:0]Acc;
reg Done;
reg[15:0]Acc;
reg[0:1] Mpy_State;
r
test.v
module Test;
reg clock,updn;
wire[0:3]cnt_out;
countupdown c1(clock,cnt_out,updn);
always #1 clock=~clock;
initial begin
clock=0;
updn=0;
#50 updn=1;
#100 $dumpflush;
$stop;
end
ini
fenpin2.v
module fenpin2(clk,reset,clk_out);
input clk,reset;
output clk_out;
wire clk_tmp1;
reg clk_tmp2,clk_tmp;
reg [2:0]count;
assign clk_tmp1=clk^clk_tmp2;
assign clk_out=clk_tmp;
decode4_7.v
module decode4_7(decodeout,indec);
input [3:0]indec;
output [6:0] decodeout;
reg [6:0] decodeout;
always@(indec)
begin
case(indec)