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V 的代码
instruction_memory.v
module instruction_memory(clk, instruction, addr, read, enable); //it's a rom, output 4 sequential bytes beginning at address of addr
input clk;
input[31:0] addr;
input read, enable;
output re
cputop.v
`timescale 1ns/10ps
`define PERIOD 100
module cputop;
reg clk;
reg reset;
initial
begin
clk = 1;
system_reset;
end
pipelinedCPU CPU_instance(.clk(clk), .reset(rese
cpld_qq2812.v
//0x4000:一般外设,0x4000,A13:0,A12:0
//0x2000:SL811,0x2000,A13:1,A12:0
//0x5000:RTL8019,0x5000,A13:0,A12:1
/*下面是对外设的各个地址进行了宏定义*/
//Read Add
`define INT1Add 6'h01
`define NMIAdd
traffic_light_controller2.v
//***************************************************
// File Name: traffic_light_controller.v
// Date: October7,2008
// author: yilong.you
// yilong.you@stu.xjtu.edu.cn
//******
myrom.v
`timescale 1ns/10ps
module myrom(read_data,addr,read_en_);
input read_en_;
input[3:0]addr;
output [3:0]read_data;
reg [3:0]read_data;
reg[3:0]mem[0:15];
initial
$readmemb("my_rom_data",mem);
alway
clk_gen.v
module clk_gen(clk);
output clk;
reg clk;
`include"common.txt"
initial begin
while($time
has_task.v
module Has_Task;
parameter MAXBITS=8;
task Revers_Bits;
input [MAXBITS-1:0]Din;
output [MAXBITS-1:0]Dout;l
integer k;
begin
for(k=0;k
wave2.v
`timescale 10ns/1ns
module wave2;
reg wave;
parameter cycle=5;
initial fork
wave=0;
#(cycle) wave=1;
#(2*cycle) wave=0;
#(3*cycle) wave=1;
#(4*cycle) wave=0;
#(5*cycle)
bin27seg.v
//
//
//-----------------------------------------------------------------------------------
// DESCRIPTION : BIN to seven segments converter
// segment encoding
//
countu3d5.v
module countu3d5(rst, clk, up, dn, din, dout, par, carry, borrow);
input rst, clk, up, dn;
input [7:0] din;
output [7:0] dout;
output par, carry, borrow;
reg [7:0] dout;
reg par, carry, borrow;