and.v

將Verilog設計轉成VHDL設計的程式

module AND(in1, in2, out);
  //Structural model of AND gate from two NANDS
  input in1, in2;
  output out;
  wire w1;
  // two instances of the module NAND
  NAND NAND1(in1, in2, w1);
  NAND NAND2(w1, w1, out);


endmodule