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V 的代码
h_gen.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
acounter.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
nfcm_top.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
ebr_buffer.v
/* Verilog netlist generated by SCUBA ispLever_v72_PROD_Build (44) */
/* Module Version: 7.0 */
/* C:\ispTOOLS7_2\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch mj5g00
ebr_buffer.v
/* Verilog netlist generated by SCUBA ispLever_v8.0_PROD_Build (39) */
/* Module Version: 7.1 */
/* d:\ispTOOLS8_0\ispfpga\bin\nt\scuba.exe -w -lang verilog -synth synplify -bus_exp 7 -bb -arch mg5a00
errloc.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
md.v
/******************************************************************************
*
* File Name: md.v
* Version: 1.1
* Date: January 22, 2000
* Model: Manchester Decoder
*
*
md_tf.v
/* Testfixture for Manchester decoder
Xilinx, Inc
Jan 26, 2000 */
'timescale 1 ns / 1 ns
module md_tf ;
reg rst ;
reg clk16x ;
reg mdi ;
reg clk1x_enable ;
reg clk1x ;
reg nrz ;
reg [3:0] no_
me_tf.v
`timescale 1 ns / 1 ns
module me_tf ;
reg [7:0] din ;
reg rst ;
reg clk ;
reg wr ;
wire mdo ;
wire ready ;
me u1 (rst,clk,wr,din,ready,mdo) ;
initial begin
rst = 1'b0 ;
clk = 1'b0 ;
din = 8'h0 ;
wr
me.v
/******************************************************************************
*
* File Name: me.v
* Version: 1.0
* Date: January 22, 2000
* Model: Manchester Encoder Chip