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eth_maccontrol.v
`include "timescale.v"
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxD
eth_shiftreg.v
`include "timescale.v"
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
parameter Tp
eth_register.v
`include "timescale.v"
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
in
wb_master32.v
`include "wb_model_defines.v"
`include "timescale.v"
module WB_MASTER32
(
CLK_I,
RST_I,
TAG_I,
TAG_O,
ACK_I,
ADR_O,
CYC_O,
DAT_I,
DAT_O,
ERR_I,
eth_rxethmac.v
//
//
//
`include "timescale.v"
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm,
tb_eth_top.v
Please use tb_ethernet.v for testbench. Testbench will soon be
updated.
//////////////////////////////////////////////////////////////////////
`in
tb_cop.v
`include "timescale.v"
module tb_cop();
parameter Tp = 1;
reg wb_clk_o;
reg wb_rst_o;
// WISHBONE master 1 (input)
reg [31:0] m1_wb_adr_o;
reg [3:0] m1
eth_wishbone.v
`include "eth_defines.v"
`include "timescale.v"
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK
eth_phy.v
`include "timescale.v"
`include "eth_phy_defines.v"
`include "tb_eth_defines.v"
module eth_phy // This PHY model simulate simplified Intel LXT971A PHY
(
// COMMON
m_rst_n_i,
eth_fifo.v
`include "eth_defines.v"
`include "timescale.v"
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 3