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V 的代码
eth_host.v
`include "tb_eth_defines.v"
`include "timescale.v"
module eth_host
(
// WISHBONE common
wb_clk_i, wb_rst_i,
// WISHBONE master
wb_adr_o, wb_sel_o, wb_we_o, wb_dat_i, wb_dat_o
eth_txcounters.v
`include "timescale.v"
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, Sta
eth_outputcontrol.v
`include "timescale.v"
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
parameter Tp = 1;
input Clk; /
wb_master_behavioral.v
/
`include "wb_model_defines.v"
`include "timescale.v"
module WB_MASTER_BEHAVIORAL
(
CLK_I,
RST_I,
TAG_I,
TAG_O,
ACK_I,
ADR_O,
CYC_O,
DAT_I,
DAT_O,
eth_rxcounters.v
`include "timescale.v"
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmit
eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
eth_cop.v
`include "tb_eth_defines.v"
`include "timescale.v"
module eth_cop
(
// WISHBONE common
wb_clk_i, wb_rst_i,
// WISHBONE MASTER 1
m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_d
top_tb.v
`timescale 1ns/1ns
module top_tb;
reg clk;
reg rst_n;
wire [7:0] wAD;
reg [7:0] rAD;
reg [7:0] addr;
reg wr_n
uart.v
/*********************************************************************************************************
** All right reserve 2008-2009(C)
**
txd.v
/*********************************************************************************************************
** All right reserve 2008-2009(C)
**