代码搜索：vhdl
找到约 10,000 项符合「vhdl」的源代码
代码结果 10,000
www.eeworm.com/read/16360/670383
asm _vhdl.asm
www.eeworm.com/read/16360/670385
asm _vhdl.asm
www.eeworm.com/read/16360/670399
vhdl fenping.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity fenping is
port(clk:in std_logic;
clks1:out std_logic);
end;
Architect
www.eeworm.com/read/16360/670404
vhdl minute.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity minute1 is
Port(clkm, reset:in std_logic;
--M1:in std_logic_vector(7 downt
www.eeworm.com/read/16360/670418
vhdl yima.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity yima is
Port(sec1,sec2,min1,min2,hou1,hou2: in std_logic_vector(3 downto 0);
www.eeworm.com/read/16360/670459
vhdl alm.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity alarm1 is
Port(reset:in std_logic;
Min1,min2:in std_logic_vect
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vhdl second.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity second1 is
Port(clks, reset:in std_logic;
--S1:in std_logic_vector(7 downt
www.eeworm.com/read/16360/670570
vhdl hour.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour11 is
Port(clkh,reset:in std_logic;
--h1:in std_logic_vector(7 downto
www.eeworm.com/read/16360/670612
vhdl jhgjgh.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
www.eeworm.com/read/17625/743538
vhdl test.vhdl
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acquistion is
port
(
vcc,tclk0,reset,vref,href,llc2: in std_logic;
outer,outer