second.vhdl

来自「EDA课程设计（带完整设计报告）」· VHDL 代码 · 共 36 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity second1 is
 Port(clks, reset:in std_logic;
      --S1:in std_logic_vector(7 downto 0);            ――置数端（秒）
      Sec1,sec2:buffer std_logic_vector(3 downto 0);       --秒输出端
      Ensec:out std_logic);             --秒计时器的进位，用来驱动分计时器
End;
Architecture a of second1 is
  Begin
 Process(clks,reset)
  Begin
   If reset='0' then 
     Sec1<="0000"; 
     Sec2<="0000";
     ensec<='0';           --对秒计时器清0
   --Elsif set='0' then sec<=s1;                   ――对秒计时器置s1的数
   Elsif clks'event and clks='1' then
         if (sec1= "1001" and sec2= "0101") then
                     Sec1<="0000"; 
                            Sec2<="0000";
                                 ensec<='1';    --重复计数并产生进位     
         elsif (sec1= "1001")then
	             Sec1<="0000";
	              Sec2<=sec2+1;	   
                    ensec<='0'; 
	   else
		              sec1<=sec1+1;
                  ensec<='0';       --以驱动下一级
	   end if;	
 end if;
End process;
End;