minute.vhdl

来自「EDA课程设计（带完整设计报告）」· VHDL 代码 · 共 36 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity minute1 is
 Port(clkm, reset:in std_logic;
      --M1:in std_logic_vector(7 downto 0);            ――置数端（秒）
      Min1,Min2:buffer std_logic_vector(3 downto 0);       --秒输出端
      Enmin:out std_logic);              --秒计时器的进位，用来驱动分计时器
End;
Architecture a of minute1 is
  Begin
 Process(clkm,reset )
  Begin
   If reset='0' then 
Min1<="0000"; 
Min2<="0000";
enmin<='0';                   --对计时器清0
   --Elsif set='0' then sec<=s1;                   ――对秒计时器置s1的数
   Elsif clkm'event and clkm='1' then
    if (Min1= "1001" and Min2= "0101") then
    Min1<="0000"; 
Min2<="0000";
enmin<='1';    --重复计数并产生进位     
elsif (Min1= "1001")then
	     Min1<="0000";
	     Min2<= Min2+1;	   
         enmin<='0'; 
	   else
		  min1<=min1+1;
        enmin<='0';       --以驱动下一级
	   end if;	
 end if;
End process;
End;