fenping.vhdl

EDA课程设计（带完整设计报告）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity fenping is
port(clk:in std_logic;
     clks1:out std_logic);
end;

Architecture aa of fenping is
begin
signal cnt:integer:=0;
signal clks : std_logic :='0';
process(clk)
  begin
  if reset = '0' then
     clks<= '0';
      if(clk'event and clk='1')then   
           if cnt=16000000 then
              --if cnt=10 then
               cnt<=0;
	           clks<=not(clks);	
          else
	          cnt<=cnt+1;
            end if;
  end if;
  end process;
  end;