jhgjgh.vhdl

来自「EDA课程设计（带完整设计报告）」· VHDL 代码 · 共 40 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jhgjgh is
port(clk,reset:in std_logic;
      q:out std_logic);
end jhgjgh;

architecture Behavioral of jhgjgh is
signal cnt:integer:=0;
signal clks:std_logic:='0';
begin
process(clk,reset)
  begin
  if reset = '0' then
     clks<= '0';
  elsif(clk'event and clk='1')then   
           if cnt=16000000 then
              --if cnt=10 then
               cnt<=0;
	          clks<=not(clks);	
          else
	          cnt<=cnt+1;
			clks<=clks;
            end if;
  
  end if;
end process;
q<=clks;


end Behavioral;