hour.vhdl

来自「EDA课程设计（带完整设计报告）」· VHDL 代码 · 共 36 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity hour11 is
 Port(clkh,reset:in std_logic;
      --h1:in std_logic_vector(7 downto 0);              ――置数端（时）
      Hour1,hour2:buffer std_logic_vector(3 downto 0));         --时输出端
      --Enhour:out std_logic);              --时计时器的进位，用来驱动星期计时器
End;
Architecture a of hour11 is
  Begin
 Process(clkh,reset)
  Begin
   If reset='0' then
      hour1<="0000"; 
      hour2<="0000"; 
	 --Enhour<='0';            --对时计时器清0
   -- Elsif set='0' then hour<=h1;                  ――对时计时器置h1的数
   Elsif clkh'event and clkh='1' then
       if (hour1= "0011" and hour2= "0010") then
              hour1<="0000"; 
              hour2<="0000";
		    --Enhour<='1'; --重复计数       
       elsif (hour1= "1001")then
	         hour1<="0000";
	         hour2<=hour2+1;
		    --Enhour<='0';	   
       else
		  hour1<=hour1+1;
		  --Enhour<='0';
       end if;      
 end if;
End process;
End;