test.vhdl

CPLD初始化程序-用于DSP5416与SAA7111A的时序控制初始化

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acquistion is 
port
(
vcc,tclk0,reset,vref,href,llc2: in std_logic;
outer,outer2,outer3,outer4: out std_logic
);
end acquistion;
architecture structure of acquistion is
--signal sig_save1: std_logic;
--signal sig_save2: std_logic;
signal q1,q2,s1,s2,divclk1,divclk2,a1,a2: std_logic;
signal count:std_logic_vector(1 downto 0 );
signal tempdivclk1:std_logic:='0';
signal tempdivclk2:std_logic:='0';
begin
process(reset,q2,tclk0,vcc,s1)
begin

--change position
s2<=not reset;
--change expression
s1<=s2 or q2;

--*/D触发器1/*--
if(s1='1')then
q1<='0';
elsif( tclk0'event and tclk0='1')then
q1<=vcc;
end if;
end process;
--if( tclk0'event and tclk0='1')then
--if(s1='1')then
 --  sig_save1<='0';
-- else 
--   sig_save1<=vcc; 
--end if;
--q1<=sig_save1;
--end process;

--*/D触发器2/*--
process(q1,vref,s2)
begin
if(s2='1')then
q2<='0';
elsif(  vref'event and vref='1')then
q2<=q1;
end if;
end process;
--if( vref'event and vref='1')then
 --if(s2='1')then
--   sig_save2<='0';
-- else 
--   sig_save2<=q1; 
--end if;
--q2<=sig_save2;
--end process;


--*/href分频/*--
process(href)
begin
if(href'event and href='1')then
--change mode for program
    tempdivclk1<=not tempdivclk1;
 end if;
--change position
divclk1<=tempdivclk1;
end process;

--*LLC2分频/*-- 
process(llc2)
    begin 
       if(llc2'event and llc2 ='1')then
           if(count="11")then
              count<=(others=>'0');
           else
              count<=count+1;
           end if;
       end if;
outer4 <= not count(1);
end process;

process(llc2)
begin
if(llc2'event and llc2='1')then
--change mode for program
    tempdivclk2<=not tempdivclk2;
 end if;
--change position
divclk2<=tempdivclk2;
end process;

a1<=href and divclk1;
a2<=llc2 and divclk2;
--add 'not'
outer<=q2 and a1 and (not count(1));
outer2<=divclk2;
outer3<=a2;
end structure;