代码搜索:vhdl

找到约 10,000 项符合「vhdl」的源代码

代码结果 10,000
www.eeworm.com/read/2252/14952

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 23:15:07 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity \74lvth245\ is port ( A1: IN STD_LOGIC; A2:
www.eeworm.com/read/2252/14969

vhd vhdl.vhd

-- generated by newgenasym Tue Nov 04 09:34:15 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity timer is port ( CONT: IN STD_LOGIC; DISCH: IN
www.eeworm.com/read/2252/14986

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 23:13:05 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity ltc4242c is port ( AUXFAULT1_N: OUT STD_LOGIC; AUXFAULT2_N
www.eeworm.com/read/2252/15003

vhd vhdl.vhd

-- generated by newgenasym Tue Nov 04 09:34:48 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity \74lvth125\ is port ( A1: IN STD_LOGIC; A2:
www.eeworm.com/read/2252/15020

vhd vhdl.vhd

-- generated by newgenasym Tue Oct 21 18:34:25 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity lm317 is port ( ADJ: IN STD_LOGIC; \in\: IN
www.eeworm.com/read/2252/15038

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 23:14:11 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity \74lvth244\ is port ( \1a1\: IN STD_LOGIC; \1a2\:
www.eeworm.com/read/2252/15059

vhd vhdl.vhd

-- generated by newgenasym Tue Nov 04 14:14:40 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity MPC8641D is port ( AGND_SRDS1: IN STD_LOGIC; AGND_SRDS2:
www.eeworm.com/read/2252/15082

vhd vhdl.vhd

-- generated by newgenasym Fri Oct 24 14:14:46 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity dg419 is port ( GND: IN STD_LOGIC; INA1: IN
www.eeworm.com/read/2252/15099

vhd vhdl.vhd

-- generated by newgenasym Fri Oct 24 14:59:30 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity opampadj is port ( M: IN STD_LOGIC; N1: OU
www.eeworm.com/read/2252/15116

vhd vhdl.vhd

-- generated by newgenasym Tue Oct 28 15:34:22 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity mt47j64m16 is port ( A0: IN STD_LOGIC; A1: