vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Tue Nov 04 09:34:48 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvth125\ is
    port (    
	A1:        IN     STD_LOGIC;    
	A2:        IN     STD_LOGIC;    
	A3:        IN     STD_LOGIC;    
	A4:        IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	OE1_N:     OUT    STD_LOGIC;    
	OE2_N:     OUT    STD_LOGIC;    
	OE3_N:     OUT    STD_LOGIC;    
	OE4_N:     OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	Y1:        OUT    STD_LOGIC;    
	Y2:        OUT    STD_LOGIC;    
	Y3:        OUT    STD_LOGIC;    
	Y4:        OUT    STD_LOGIC);
end \74lvth125\;