vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Tue Nov 04 14:14:40 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity MPC8641D is
    port (    
	AGND_SRDS1: IN     STD_LOGIC;    
	AGND_SRDS2: IN     STD_LOGIC;    
	ASLEEP:    OUT    STD_LOGIC;    
	AVDD_CORE0: IN     STD_LOGIC;    
	AVDD_CORE1: IN     STD_LOGIC;    
	AVDD_LB:   IN     STD_LOGIC;    
	AVDD_PLAT: IN     STD_LOGIC;    
	AVDD_SRDS1: IN     STD_LOGIC;    
	AVDD_SRDS2: IN     STD_LOGIC;    
	\ckstp_in*\: IN     STD_LOGIC;    
	\ckstp_out*\: OUT    STD_LOGIC;    
	CLK_OUT:   OUT    STD_LOGIC;    
	D1_MA0:    OUT    STD_LOGIC;    
	D1_MA1:    OUT    STD_LOGIC;    
	D1_MA10:   OUT    STD_LOGIC;    
	D1_MA11:   OUT    STD_LOGIC;    
	D1_MA12:   OUT    STD_LOGIC;    
	D1_MA13:   OUT    STD_LOGIC;    
	D1_MA14:   OUT    STD_LOGIC;    
	D1_MA15:   OUT    STD_LOGIC;    
	D1_MA2:    OUT    STD_LOGIC;    
	D1_MA3:    OUT    STD_LOGIC;    
	D1_MA4:    OUT    STD_LOGIC;    
	D1_MA5:    OUT    STD_LOGIC;    
	D1_MA6:    OUT    STD_LOGIC;    
	D1_MA7:    OUT    STD_LOGIC;    
	D1_MA8:    OUT    STD_LOGIC;    
	D1_MA9:    OUT    STD_LOGIC;    
	D1_MBA0:   OUT    STD_LOGIC;    
	D1_MBA1:   OUT    STD_LOGIC;    
	D1_MBA2:   OUT    STD_LOGIC;    
	\d1_mcas*\: OUT    STD_LOGIC;    
	D1_MCK0:   OUT    STD_LOGIC;    
	\d1_mck0*\: OUT    STD_LOGIC;    
	D1_MCK1:   OUT    STD_LOGIC;    
	\d1_mck1*\: OUT    STD_LOGIC;    
	D1_MCK2:   OUT    STD_LOGIC;    
	\d1_mck2*\: OUT    STD_LOGIC;    
	D1_MCK3:   OUT    STD_LOGIC;    
	\d1_mck3*\: OUT    STD_LOGIC;    
	D1_MCK4:   OUT    STD_LOGIC;    
	\d1_mck4*\: OUT    STD_LOGIC;    
	D1_MCK5:   OUT    STD_LOGIC;    
	\d1_mck5*\: OUT    STD_LOGIC;    
	D1_MCKE0:  OUT    STD_LOGIC;    
	D1_MCKE1:  OUT    STD_LOGIC;    
	D1_MCKE2:  OUT    STD_LOGIC;    
	D1_MCKE3:  OUT    STD_LOGIC;    
	\d1_mcs0*\: OUT    STD_LOGIC;    
	\d1_mcs1*\: OUT    STD_LOGIC;    
	\d1_mcs2*\: OUT    STD_LOGIC;    
	\d1_mcs3*\: OUT    STD_LOGIC;    
	D1_MDIC0:  INOUT  STD_LOGIC;    
	D1_MDIC1:  INOUT  STD_LOGIC;    
	D1_MDM0:   OUT    STD_LOGIC;    
	D1_MDM1:   OUT    STD_LOGIC;    
	D1_MDM2:   OUT    STD_LOGIC;    
	D1_MDM3:   OUT    STD_LOGIC;    
	D1_MDM4:   OUT    STD_LOGIC;    
	D1_MDM5:   OUT    STD_LOGIC;    
	D1_MDM6:   OUT    STD_LOGIC;    
	D1_MDM7:   OUT    STD_LOGIC;    
	D1_MDM8:   OUT    STD_LOGIC;    
	D1_MDQ0:   INOUT  STD_LOGIC;    
	D1_MDQ1:   INOUT  STD_LOGIC;    
	D1_MDQ10:  INOUT  STD_LOGIC;    
	D1_MDQ11:  INOUT  STD_LOGIC;    
	D1_MDQ12:  INOUT  STD_LOGIC;    
	D1_MDQ13:  INOUT  STD_LOGIC;    
	D1_MDQ14:  INOUT  STD_LOGIC;    
	D1_MDQ15:  INOUT  STD_LOGIC;    
	D1_MDQ16:  INOUT  STD_LOGIC;    
	D1_MDQ17:  INOUT  STD_LOGIC;    
	D1_MDQ18:  INOUT  STD_LOGIC;    
	D1_MDQ19:  INOUT  STD_LOGIC;    
	D1_MDQ2:   INOUT  STD_LOGIC;    
	D1_MDQ20:  INOUT  STD_LOGIC;    
	D1_MDQ21:  INOUT  STD_LOGIC;    
	D1_MDQ22:  INOUT  STD_LOGIC;    
	D1_MDQ23:  INOUT  STD_LOGIC;    
	D1_MDQ24:  INOUT  STD_LOGIC;    
	D1_MDQ25:  INOUT  STD_LOGIC;    
	D1_MDQ26:  INOUT  STD_LOGIC;    
	D1_MDQ27:  INOUT  STD_LOGIC;    
	D1_MDQ28:  INOUT  STD_LOGIC;    
	D1_MDQ29:  INOUT  STD_LOGIC;    
	D1_MDQ3:   INOUT  STD_LOGIC;    
	D1_MDQ30:  INOUT  STD_LOGIC;    
	D1_MDQ31:  INOUT  STD_LOGIC;    
	D1_MDQ32:  INOUT  STD_LOGIC;    
	D1_MDQ33:  INOUT  STD_LOGIC;    
	D1_MDQ34:  INOUT  STD_LOGIC;    
	D1_MDQ35:  INOUT  STD_LOGIC;    
	D1_MDQ36:  INOUT  STD_LOGIC;    
	D1_MDQ37:  INOUT  STD_LOGIC;    
	D1_MDQ38:  INOUT  STD_LOGIC;    
	D1_MDQ39:  INOUT  STD_LOGIC;    
	D1_MDQ4:   INOUT  STD_LOGIC;    
	D1_MDQ40:  INOUT  STD_LOGIC;    
	D1_MDQ41:  INOUT  STD_LOGIC;    
	D1_MDQ42:  INOUT  STD_LOGIC;    
	D1_MDQ43:  INOUT  STD_LOGIC;    
	D1_MDQ44:  INOUT  STD_LOGIC;    
	D1_MDQ45:  INOUT  STD_LOGIC;    
	D1_MDQ46:  INOUT  STD_LOGIC;    
	D1_MDQ47:  INOUT  STD_LOGIC;    
	D1_MDQ48:  INOUT  STD_LOGIC;    
	D1_MDQ49:  INOUT  STD_LOGIC;    
	D1_MDQ5:   INOUT  STD_LOGIC;    
	D1_MDQ50:  INOUT  STD_LOGIC;    
	D1_MDQ51:  INOUT  STD_LOGIC;    
	D1_MDQ52:  INOUT  STD_LOGIC;    
	D1_MDQ53:  INOUT  STD_LOGIC;    
	D1_MDQ54:  INOUT  STD_LOGIC;    
	D1_MDQ55:  INOUT  STD_LOGIC;    
	D1_MDQ56:  INOUT  STD_LOGIC;    
	D1_MDQ57:  INOUT  STD_LOGIC;    
	D1_MDQ58:  INOUT  STD_LOGIC;    
	D1_MDQ59:  INOUT  STD_LOGIC;    
	D1_MDQ6:   INOUT  STD_LOGIC;    
	D1_MDQ60:  INOUT  STD_LOGIC;    
	D1_MDQ61:  INOUT  STD_LOGIC;    
	D1_MDQ62:  INOUT  STD_LOGIC;    
	D1_MDQ63:  INOUT  STD_LOGIC;    
	D1_MDQ7:   INOUT  STD_LOGIC;    
	D1_MDQ8:   INOUT  STD_LOGIC;    
	D1_MDQ9:   INOUT  STD_LOGIC;    
	D1_MDQS0:  INOUT  STD_LOGIC;    
	\d1_mdqs0*\: INOUT  STD_LOGIC;    
	D1_MDQS1:  INOUT  STD_LOGIC;    
	\d1_mdqs1*\: INOUT  STD_LOGIC;    
	D1_MDQS2:  INOUT  STD_LOGIC;    
	\d1_mdqs2*\: INOUT  STD_LOGIC;    
	D1_MDQS3:  INOUT  STD_LOGIC;    
	\d1_mdqs3*\: INOUT  STD_LOGIC;    
	D1_MDQS4:  INOUT  STD_LOGIC;    
	\d1_mdqs4*\: INOUT  STD_LOGIC;    
	D1_MDQS5:  INOUT  STD_LOGIC;    
	\d1_mdqs5*\: INOUT  STD_LOGIC;    
	D1_MDQS6:  INOUT  STD_LOGIC;    
	\d1_mdqs6*\: INOUT  STD_LOGIC;    
	D1_MDQS7:  INOUT  STD_LOGIC;    
	\d1_mdqs7*\: INOUT  STD_LOGIC;    
	D1_MDQS8:  INOUT  STD_LOGIC;    
	\d1_mdqs8*\: INOUT  STD_LOGIC;    
	D1_MDVAL_LB_DVAL: OUT    STD_LOGIC;    
	D1_MECC0:  INOUT  STD_LOGIC;    
	D1_MECC1:  INOUT  STD_LOGIC;    
	D1_MECC2:  INOUT  STD_LOGIC;    
	D1_MECC3:  INOUT  STD_LOGIC;    
	D1_MECC4:  INOUT  STD_LOGIC;    
	D1_MECC5:  INOUT  STD_LOGIC;    
	D1_MECC6:  INOUT  STD_LOGIC;    
	D1_MECC7:  INOUT  STD_LOGIC;    
	D1_MODT0:  OUT    STD_LOGIC;    
	D1_MODT1:  OUT    STD_LOGIC;    
	D1_MODT2:  OUT    STD_LOGIC;    
	D1_MODT3:  OUT    STD_LOGIC;    
	\d1_mras*\: OUT    STD_LOGIC;    
	D1_MSRCID1_LB_SRCID1: OUT    STD_LOGIC;    
	D1_MSRCID2_LB_SRCID2: OUT    STD_LOGIC;    
	D1_MSRCID3_LB_SRCID3: OUT    STD_LOGIC;    
	D1_MSRCID4_LB_SRCID4: OUT    STD_LOGIC;    
	D1_MSRCID_LB_SRCID0: OUT    STD_LOGIC;    
	D1_MVREF:  IN     STD_LOGIC;    
	\d1_mwe*\: OUT    STD_LOGIC;    
	D2_MA0:    OUT    STD_LOGIC;    
	D2_MA1:    OUT    STD_LOGIC;    
	D2_MA10:   OUT    STD_LOGIC;    
	D2_MA11:   OUT    STD_LOGIC;    
	D2_MA12:   OUT    STD_LOGIC;    
	D2_MA13:   OUT    STD_LOGIC;    
	D2_MA14:   OUT    STD_LOGIC;    
	D2_MA15:   OUT    STD_LOGIC;    
	D2_MA2:    OUT    STD_LOGIC;    
	D2_MA3:    OUT    STD_LOGIC;    
	D2_MA4:    OUT    STD_LOGIC;    
	D2_MA5:    OUT    STD_LOGIC;    
	D2_MA6:    OUT    STD_LOGIC;    
	D2_MA7:    OUT    STD_LOGIC;    
	D2_MA8:    OUT    STD_LOGIC;    
	D2_MA9:    OUT    STD_LOGIC;    
	D2_MBA0:   OUT    STD_LOGIC;    
	D2_MBA1:   OUT    STD_LOGIC;    
	D2_MBA2:   OUT    STD_LOGIC;    
	\d2_mcas*\: OUT    STD_LOGIC;    
	D2_MCK0:   OUT    STD_LOGIC;    
	\d2_mck0*\: OUT    STD_LOGIC;    
	D2_MCK1:   OUT    STD_LOGIC;    
	\d2_mck1*\: OUT    STD_LOGIC;    
	D2_MCK2:   OUT    STD_LOGIC;    
	\d2_mck2*\: OUT    STD_LOGIC;    
	D2_MCK3:   OUT    STD_LOGIC;    
	\d2_mck3*\: OUT    STD_LOGIC;    
	D2_MCK4:   OUT    STD_LOGIC;    
	\d2_mck4*\: OUT    STD_LOGIC;    
	D2_MCK5:   OUT    STD_LOGIC;    
	\d2_mck5*\: OUT    STD_LOGIC;    
	D2_MCKE0:  OUT    STD_LOGIC;    
	D2_MCKE1:  OUT    STD_LOGIC;    
	D2_MCKE2:  OUT    STD_LOGIC;    
	D2_MCKE3:  OUT    STD_LOGIC;    
	\d2_mcs0*\: OUT    STD_LOGIC;    
	\d2_mcs1*\: OUT    STD_LOGIC;    
	\d2_mcs2*\: OUT    STD_LOGIC;    
	\d2_mcs3*\: OUT    STD_LOGIC;    
	D2_MDIC0:  INOUT  STD_LOGIC;    
	D2_MDIC1:  INOUT  STD_LOGIC;    
	D2_MDM0:   OUT    STD_LOGIC;    
	D2_MDM1:   OUT    STD_LOGIC;    
	D2_MDM2:   OUT    STD_LOGIC;    
	D2_MDM3:   OUT    STD_LOGIC;    
	D2_MDM4:   OUT    STD_LOGIC;    
	D2_MDM5:   OUT    STD_LOGIC;    
	D2_MDM6:   OUT    STD_LOGIC;    
	D2_MDM7:   OUT    STD_LOGIC;    
	D2_MDM8:   OUT    STD_LOGIC;    
	D2_MDQ0:   INOUT  STD_LOGIC;    
	D2_MDQ1:   INOUT  STD_LOGIC;    
	D2_MDQ10:  INOUT  STD_LOGIC;    
	D2_MDQ11:  INOUT  STD_LOGIC;    
	D2_MDQ12:  INOUT  STD_LOGIC;    
	D2_MDQ13:  INOUT  STD_LOGIC;    
	D2_MDQ14:  INOUT  STD_LOGIC;    
	D2_MDQ15:  INOUT  STD_LOGIC;    
	D2_MDQ16:  INOUT  STD_LOGIC;    
	D2_MDQ17:  INOUT  STD_LOGIC;    
	D2_MDQ18:  INOUT  STD_LOGIC;    
	D2_MDQ19:  INOUT  STD_LOGIC;    
	D2_MDQ2:   INOUT  STD_LOGIC;    
	D2_MDQ20:  INOUT  STD_LOGIC;    
	D2_MDQ21:  INOUT  STD_LOGIC;    
	D2_MDQ22:  INOUT  STD_LOGIC;    
	D2_MDQ23:  INOUT  STD_LOGIC;    
	D2_MDQ24:  INOUT  STD_LOGIC;    
	D2_MDQ25:  INOUT  STD_LOGIC;    
	D2_MDQ26:  INOUT  STD_LOGIC;    
	D2_MDQ27:  INOUT  STD_LOGIC;    
	D2_MDQ28:  INOUT  STD_LOGIC;    
	D2_MDQ29:  INOUT  STD_LOGIC;    
	D2_MDQ3:   INOUT  STD_LOGIC;    
	D2_MDQ30:  INOUT  STD_LOGIC;    
	D2_MDQ31:  INOUT  STD_LOGIC;    
	D2_MDQ32:  INOUT  STD_LOGIC;    
	D2_MDQ33:  INOUT  STD_LOGIC;    
	D2_MDQ34:  INOUT  STD_LOGIC;    
	D2_MDQ35:  INOUT  STD_LOGIC;    
	D2_MDQ36:  INOUT  STD_LOGIC;    
	D2_MDQ37:  INOUT  STD_LOGIC;    
	D2_MDQ38:  INOUT  STD_LOGIC;    
	D2_MDQ39:  INOUT  STD_LOGIC;    
	D2_MDQ4:   INOUT  STD_LOGIC;    
	D2_MDQ40:  INOUT  STD_LOGIC;    
	D2_MDQ41:  INOUT  STD_LOGIC;    
	D2_MDQ42:  INOUT  STD_LOGIC;    
	D2_MDQ43:  INOUT  STD_LOGIC;    
	D2_MDQ44:  INOUT  STD_LOGIC;    
	D2_MDQ45:  INOUT  STD_LOGIC;    
	D2_MDQ46:  INOUT  STD_LOGIC;    
	D2_MDQ47:  INOUT  STD_LOGIC;    
	D2_MDQ48:  INOUT  STD_LOGIC;    
	D2_MDQ49:  INOUT  STD_LOGIC;    
	D2_MDQ5:   INOUT  STD_LOGIC;    
	D2_MDQ50:  INOUT  STD_LOGIC;    
	D2_MDQ51:  INOUT  STD_LOGIC;    
	D2_MDQ52:  INOUT  STD_LOGIC;    
	D2_MDQ53:  INOUT  STD_LOGIC;    
	D2_MDQ54:  INOUT  STD_LOGIC;    
	D2_MDQ55:  INOUT  STD_LOGIC;    
	D2_MDQ56:  INOUT  STD_LOGIC;    
	D2_MDQ57:  INOUT  STD_LOGIC;    
	D2_MDQ58:  INOUT  STD_LOGIC;    
	D2_MDQ59:  INOUT  STD_LOGIC;    
	D2_MDQ6:   INOUT  STD_LOGIC;    
	D2_MDQ60:  INOUT  STD_LOGIC;    
	D2_MDQ61:  INOUT  STD_LOGIC;    
	D2_MDQ62:  INOUT  STD_LOGIC;    
	D2_MDQ63:  INOUT  STD_LOGIC;    
	D2_MDQ7:   INOUT  STD_LOGIC;    
	D2_MDQ8:   INOUT  STD_LOGIC;    
	D2_MDQ9:   INOUT  STD_LOGIC;    
	D2_MDQS0:  INOUT  STD_LOGIC;    
	\d2_mdqs0*\: INOUT  STD_LOGIC;    
	D2_MDQS1:  INOUT  STD_LOGIC;    
	\d2_mdqs1*\: INOUT  STD_LOGIC;    
	D2_MDQS2:  INOUT  STD_LOGIC;    
	\d2_mdqs2*\: INOUT  STD_LOGIC;    
	D2_MDQS3:  INOUT  STD_LOGIC;    
	\d2_mdqs3*\: INOUT  STD_LOGIC;    
	D2_MDQS4:  INOUT  STD_LOGIC;    
	\d2_mdqs4*\: INOUT  STD_LOGIC;    
	D2_MDQS5:  INOUT  STD_LOGIC;    
	\d2_mdqs5*\: INOUT  STD_LOGIC;    
	D2_MDQS6:  INOUT  STD_LOGIC;    
	\d2_mdqs6*\: INOUT  STD_LOGIC;    
	D2_MDQS7:  INOUT  STD_LOGIC;    
	\d2_mdqs7*\: INOUT  STD_LOGIC;    
	D2_MDQS8:  INOUT  STD_LOGIC;    
	\d2_mdqs8*\: INOUT  STD_LOGIC;    
	D2_MDVAL:  OUT    STD_LOGIC;    
	D2_MECC0:  INOUT  STD_LOGIC;    
	D2_MECC1:  INOUT  STD_LOGIC;    
	D2_MECC2:  INOUT  STD_LOGIC;    
	D2_MECC3:  INOUT  STD_LOGIC;    
	D2_MECC4:  INOUT  STD_LOGIC;    
	D2_MECC5:  INOUT  STD_LOGIC;    
	D2_MECC6:  INOUT  STD_LOGIC;    
	D2_MECC7:  INOUT  STD_LOGIC;    
	D2_MODT0:  OUT    STD_LOGIC;    
	D2_MODT1:  OUT    STD_LOGIC;    
	D2_MODT2:  OUT    STD_LOGIC;    
	D2_MODT3:  OUT    STD_LOGIC;    
	\d2_mras*\: OUT    STD_LOGIC;    
	D2_MSRCID0: OUT    STD_LOGIC;    
	D2_MSRCID1: OUT    STD_LOGIC;    
	D2_MSRCID2: OUT    STD_LOGIC;    
	D2_MSRCID3: OUT    STD_LOGIC;    
	D2_MSRCID4: OUT    STD_LOGIC;    
	D2_MVREF:  OUT    STD_LOGIC;