vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Wed Oct 29 23:15:07 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvth245\ is
    port (    
	A1:        IN     STD_LOGIC;    
	A2:        IN     STD_LOGIC;    
	A3:        IN     STD_LOGIC;    
	A4:        IN     STD_LOGIC;    
	A5:        IN     STD_LOGIC;    
	A6:        IN     STD_LOGIC;    
	A7:        IN     STD_LOGIC;    
	A8:        IN     STD_LOGIC;    
	B1:        OUT    STD_LOGIC;    
	B2:        OUT    STD_LOGIC;    
	B3:        OUT    STD_LOGIC;    
	B4:        OUT    STD_LOGIC;    
	B5:        OUT    STD_LOGIC;    
	B6:        OUT    STD_LOGIC;    
	B7:        OUT    STD_LOGIC;    
	B8:        OUT    STD_LOGIC;    
	DIR:       IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	OE_N:      OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74lvth245\;