vhdl.vhd

来自「Cadence_Starter_Library」· VHDL 代码 · 共 17 行

-- generated by newgenasym Fri Oct 24 14:14:46 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity dg419 is
    port (    
	GND:       IN     STD_LOGIC;    
	INA1:      IN     STD_LOGIC;    
	INA2:      IN     STD_LOGIC;    
	IND:       IN     STD_LOGIC;    
	\out\:     IN     STD_LOGIC;    
	VAN:       IN     STD_LOGIC;    
	VAP:       IN     STD_LOGIC;    
	VD:        IN     STD_LOGIC);
end dg419;