vhdl.vhd

来自「Cadence_Starter_Library」· VHDL 代码 · 共 17 行

-- generated by newgenasym Tue Nov 04 09:34:15 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity timer is
    port (    
	CONT:      IN     STD_LOGIC;    
	DISCH:     IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	\out\:     OUT    STD_LOGIC;    
	RESET:     IN     STD_LOGIC;    
	THRES:     IN     STD_LOGIC;    
	TRIG:      IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end timer;