vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Tue Oct 28 15:34:22 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity mt47j64m16 is
    port (    
	A0:        IN     STD_LOGIC;    
	A1:        IN     STD_LOGIC;    
	A10:       IN     STD_LOGIC;    
	A11:       IN     STD_LOGIC;    
	A12:       IN     STD_LOGIC;    
	A2:        IN     STD_LOGIC;    
	A3:        IN     STD_LOGIC;    
	A4:        IN     STD_LOGIC;    
	A5:        IN     STD_LOGIC;    
	A6:        IN     STD_LOGIC;    
	A7:        IN     STD_LOGIC;    
	A8:        IN     STD_LOGIC;    
	A9:        IN     STD_LOGIC;    
	BA0:       IN     STD_LOGIC;    
	BA1:       IN     STD_LOGIC;    
	BA2:       IN     STD_LOGIC;    
	\cas#\:    IN     STD_LOGIC;    
	CK:        IN     STD_LOGIC;    
	\ck#\:     IN     STD_LOGIC;    
	CKE:       IN     STD_LOGIC;    
	\cs#\:     IN     STD_LOGIC;    
	DQ0:       INOUT  STD_LOGIC;    
	DQ1:       INOUT  STD_LOGIC;    
	DQ10:      INOUT  STD_LOGIC;    
	DQ11:      INOUT  STD_LOGIC;    
	DQ12:      INOUT  STD_LOGIC;    
	DQ13:      INOUT  STD_LOGIC;    
	DQ14:      INOUT  STD_LOGIC;    
	DQ15:      INOUT  STD_LOGIC;    
	DQ2:       INOUT  STD_LOGIC;    
	DQ3:       INOUT  STD_LOGIC;    
	DQ4:       INOUT  STD_LOGIC;    
	DQ5:       INOUT  STD_LOGIC;    
	DQ6:       INOUT  STD_LOGIC;    
	DQ7:       INOUT  STD_LOGIC;    
	DQ8:       INOUT  STD_LOGIC;    
	DQ9:       INOUT  STD_LOGIC;    
	LDM:       IN     STD_LOGIC;    
	LDQS:      INOUT  STD_LOGIC;    
	\ldqs#\:   INOUT  STD_LOGIC;    
	ODT:       IN     STD_LOGIC;    
	\ras#\:    IN     STD_LOGIC;    
	RFU1:      INOUT  STD_LOGIC;    
	RFU2:      INOUT  STD_LOGIC;    
	RFU3:      INOUT  STD_LOGIC;    
	UDM:       IN     STD_LOGIC;    
	UDQS:      INOUT  STD_LOGIC;    
	\udqs#\:   INOUT  STD_LOGIC;    
	VDDL:      IN     STD_LOGIC;    
	VREF:      IN     STD_LOGIC;    
	VSSDL:     IN     STD_LOGIC;    
	\we#\:     IN     STD_LOGIC);
end mt47j64m16;