vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Wed Oct 29 23:13:05 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ltc4242c is
    port (    
	AUXFAULT1_N: OUT    STD_LOGIC;    
	AUXFAULT2_N: OUT    STD_LOGIC;    
	AUXIN1:    IN     STD_LOGIC;    
	AUXIN2:    IN     STD_LOGIC;    
	AUXON1:    IN     STD_LOGIC;    
	AUXON2:    IN     STD_LOGIC;    
	AUXOUT1:   OUT    STD_LOGIC;    
	AUXOUT2:   OUT    STD_LOGIC;    
	AUXPGOOD1_N: OUT    STD_LOGIC;    
	AUXPGOOD2_N: OUT    STD_LOGIC;    
	EN1_N:     IN     STD_LOGIC;    
	EN2_N:     IN     STD_LOGIC;    
	EPAD:      IN     STD_LOGIC;    
	FAULT1_N:  OUT    STD_LOGIC;    
	FAULT2_N:  OUT    STD_LOGIC;    
	FON1:      IN     STD_LOGIC;    
	FON2:      IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	ON1:       IN     STD_LOGIC;    
	ON2:       IN     STD_LOGIC;    
	PGOOD1_N:  OUT    STD_LOGIC;    
	PGOOD2_N:  OUT    STD_LOGIC;    
	V12_GATE1: IN     STD_LOGIC;    
	V12_GATE2: IN     STD_LOGIC;    
	V12_IN1:   IN     STD_LOGIC;    
	V12_IN2:   IN     STD_LOGIC;    
	V12_OUT1:  OUT    STD_LOGIC;    
	V12_OUT2:  OUT    STD_LOGIC;    
	V12_SENSE1: IN     STD_LOGIC;    
	V12_SENSE2: IN     STD_LOGIC;    
	V3_GATE1:  IN     STD_LOGIC;    
	V3_GATE2:  IN     STD_LOGIC;    
	V3_IN1:    IN     STD_LOGIC;    
	V3_IN2:    IN     STD_LOGIC;    
	V3_OUT1:   OUT    STD_LOGIC;    
	V3_OUT2:   OUT    STD_LOGIC;    
	V3_SENSE1: IN     STD_LOGIC;    
	V3_SENSE2: IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end ltc4242c;