vhdl.vhd

Cadence_Starter_Library

-- generated by newgenasym Wed Oct 29 23:14:11 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvth244\ is
    port (    
	\1a1\:     IN     STD_LOGIC;    
	\1a2\:     IN     STD_LOGIC;    
	\1a3\:     IN     STD_LOGIC;    
	\1a4\:     IN     STD_LOGIC;    
	\1oe_n\:   OUT    STD_LOGIC;    
	\1y1\:     OUT    STD_LOGIC;    
	\1y2\:     OUT    STD_LOGIC;    
	\1y3\:     OUT    STD_LOGIC;    
	\1y4\:     OUT    STD_LOGIC;    
	\2a1\:     IN     STD_LOGIC;    
	\2a2\:     IN     STD_LOGIC;    
	\2a3\:     IN     STD_LOGIC;    
	\2a4\:     IN     STD_LOGIC;    
	\2oe_n\:   OUT    STD_LOGIC;    
	\2y1\:     OUT    STD_LOGIC;    
	\2y2\:     OUT    STD_LOGIC;    
	\2y3\:     OUT    STD_LOGIC;    
	\2y4\:     OUT    STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74lvth244\;