代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/443250/7635375
vhd v2_52.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.Const.all;
entity V2_52 is
port(Points : in std_logic_vector(7 downto 0);
IsPass : out boolean);
end V2_52;
architecture a o
www.eeworm.com/read/443250/7635396
vhd lfsr.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use std.textio.all;
entity LFSR is
generic(BitNumber : integer := 32);
port(OutNumberA : out std_logic_vector(BitNum
www.eeworm.com/read/443250/7635403
vhd v6_5.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V6_5 is
port(a : in std_logic;
b : in std_logic;
Dout : out std_logic;
Clk : in std_log
www.eeworm.com/read/443250/7635426
vhd v9_3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Adder is
port(ManA : in std_logic_vector(24 downto 0);
ManB : in std_logic_vector(24 downto
www.eeworm.com/read/443250/7635428
vhd v9_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Flt2Fix is
port(DInA : in std_logic_vector(31 downto 0);
DInB : in std_logic_vector(31 downto 0
www.eeworm.com/read/443250/7635430
vhd v9_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Fix2Flt is
port(AddO : in std_logic_vector(24 downto 0);
DOut : out std_logic_vector(31 do
www.eeworm.com/read/443250/7635435
vhd v9_5.vhd
library ieee;
use ieee.std_logic_1164.all;
entity FltAdder is
port(DInA : in std_logic_vector(31 downto 0);
DInB : in std_logic_vector(31 downto 0);
DOut : out std_logic_vect
www.eeworm.com/read/443250/7635456
vhd v8_11.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
entity V8_11 is
port(addr : IN std_logic
www.eeworm.com/read/443250/7635477
vhd v5_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_1 is
port(Sel : in std_logic_vector(1 downto 0);
OutD : out std_logic_vector(1 downto 0));
end V5_1;
architecture a of V5_1
www.eeworm.com/read/443250/7635480
vhd v5_0.vhd
library ieee;
use ieee.std_logic_1164.all;
entity V5_0 is
port(addr : in std_logic_vector(5 downto 0);
rw : in std_logic;
a4rd : out std_logic);
end V5_0;
architectur