v5_0.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V5_0 is
port(addr	  : in std_logic_vector(5 downto 0);
     rw       : in  std_logic;
     a4rd     : out std_logic);
end V5_0;

architecture a of V5_0 is
	
begin
    
    --a4rd <= (not addr(5)) and addr(4) and (not addr(3)) and
    --        (not addr(2)) and (not addr(1)) and
    --        (not addr(0)) and rw;
    a4rd <= '1' when addr = "010000" and rw = '1' else
            '0';

          
    
end a;