v9_5.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity FltAdder is
port(DInA    : in  std_logic_vector(31 downto 0);
    DInB    : in  std_logic_vector(31 downto 0);
    DOut    : out std_logic_vector(31 downto 0);
    Clk     : in  std_logic);
end FltAdder;

architecture A_FltAdder of FltAdder is

    component Adder 
    port(ManA    : in  std_logic_vector(24 downto 0);
         ManB    : in  std_logic_vector(24 downto 0);
         IsCarry : out std_logic;
         AddO    : out std_logic_vector(24 downto 0));
    end component;
        
    component Flt2Fix 
    port(DInA   : in  std_logic_vector(31 downto 0);
         DInB   : in  std_logic_vector(31 downto 0);
         ManA   : out std_logic_vector(24 downto 0);
         ManB   : out std_logic_vector(24 downto 0);
         Exp    : out std_logic_vector(7 downto 0);
         Clk    : in  std_logic);
    end component;
        
    component Fix2Flt 
    port(AddO    : in  std_logic_vector(24 downto 0);
         DOut    : out std_logic_vector(31 downto 0);
         Exp     : in  std_logic_vector(7 downto 0);
         IsCarry : in  std_logic;
         Clk     : in  std_logic);
    end component;
    
    signal MAnA    	: std_logic_vector(24 downto 0);   
    signal MAnB    	: std_logic_vector(24 downto 0);
    signal AddO    	: std_logic_vector(24 downto 0);
    signal Exp     	: std_logic_vector(7 downto 0);
    signal IsCarry 	: std_logic;
    
begin

    UFlt2Fix : Flt2Fix
    port map(DInA => DInA,
	         DInB => DInB,
	         ManA => ManA,
	         ManB => ManB,
	         Exp  => Exp ,
	         Clk  => Clk );
	         
    UAdder : Adder
    port map(ManA    => ManA   	,
	         ManB    => ManB    ,
	         IsCarry => IsCarry , 
	         AddO    => AddO    );   
	         
    UFix2Flt : Fix2Flt       
    port map(AddO    => AddO,
	         DOut    => DOut,
	         Exp     => Exp ,
	         IsCarry => IsCarry,
	         Clk     => Clk   );


end A_FltAdder;