v2_52.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use work.Const.all;

entity V2_52 is
 port(Points		: in std_logic_vector(7 downto 0);
      IsPass 	    : out boolean);
end V2_52;

architecture a of V2_52 is
	
begin    
    IsPass <= true when Points > Threshold else
            false;      
end a;