v6_5.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V6_5 is
port(a	  : in std_logic;
     b    : in std_logic;
     Dout : out std_logic;
     Clk  : in std_logic);
end V6_5;

architecture a of V6_5 is
	
begin
    
    process
    begin
		wait until Clk = '0';
    		Dout <= a;
    	wait until Clk = '1';
    		Dout <= b;
    end process;             
    
end a;