v9_3.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity Adder is
    port(ManA    : in  std_logic_vector(24 downto 0);
         ManB    : in  std_logic_vector(24 downto 0);
         IsCarry : out std_logic;
         AddO    : out std_logic_vector(24 downto 0));
end Adder;

architecture A_Adder of Adder is
	signal AddInt : std_logic_vector(25 downto 0);
begin

	AddInt <= (ManA(ManA'left) & ManA) + (ManB(ManB'left) & ManB); 
	AddO <= AddInt(25 downto 1) when AddInt(25 downto 24) = "01" or 
	    	                         AddInt(25 downto 24) = "10" else
	        AddInt(24 downto 0);
	IsCarry <= '1' when AddInt(25 downto 24) = "01" or 
	                    AddInt(25 downto 24) = "10" else
	           '0';	        
    
end A_Adder;