v8_11.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on

entity V8_11 is
	port(addr	: IN std_logic_VECTOR(7 downto 0);
		 clk	: IN std_logic;
		 di	    : IN std_logic_VECTOR(7 downto 0);
		 we	    : IN std_logic;
		 en	    : IN std_logic;
		 rst	: IN std_logic;
	 	 do	    : OUT std_logic_VECTOR(7 downto 0));
end V8_11;

architecture A_RAMTest of V8_11 is

	component ram256
	port(addr	: IN std_logic_VECTOR(7 downto 0);
		 clk	: IN std_logic;
		 di	    : IN std_logic_VECTOR(7 downto 0);
		 we	    : IN std_logic;
		 en	    : IN std_logic;
		 rst	: IN std_logic;
	 	 do	    : OUT std_logic_VECTOR(7 downto 0));
	end component;

begin

	Uram256 : ram256
	port map(addr	=> addr	,
	         clk	=> clk	,
	         di	    => di	,	
	         we	    => we	,	
	         en	    => en	,	
	         rst	=> rst	,
	         do	    => do	);	

end A_RAMTest;

configuration CFG_RAMTest of V8_11 is
for A_RAMTest
-- synopsys translate_off
	for all : ram256 use entity XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
		generic map(
			c_has_en => 1,
			c_rst_polarity => 1,
			c_clk_polarity => 1,
			c_width => 8,
			c_has_do => 1,
			c_has_di => 1,
			c_en_polarity => 1,
			c_has_we => 1,
			c_has_rst => 1,
			c_address_width => 8,
			c_read_mif => 0,
			c_depth => 256,
			c_pipe_stages => 0,
			c_mem_init_radix => 16,
			c_default_data => "0",
			c_mem_init_file => "ram256.mif",
			c_we_polarity => 1,
			c_generate_mif => 1);
	end for;
-- synopsys translate_on
end for;
end CFG_RAMTest;