v9_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Fix2Flt is
    port(AddO   	: in  	std_logic_vector(24 downto 0);
    	 DOut   	: out  	std_logic_vector(31 downto 0);
    	 Exp    	: in  	std_logic_vector(7 downto 0);
         IsCarry 	: in  	std_logic;
         Clk     	: in  	std_logic);
end Fix2Flt;

architecture A_Fix2Flt of Fix2Flt is

    signal AbsAddO   : std_logic_vector(23 downto 0);
    signal ShiftAddO : std_logic_vector(23 downto 0);
    signal TwoComp   : std_logic_vector(22 downto 0);
    signal ExpI      : std_logic_vector(7 downto 0);
    signal CarryOut  : std_logic_vector(4 downto 0);
    signal SignO     : std_logic;

begin
    SignO <= AddO(24);
    ExpI <= Exp + IsCarry - CarryOut when AbsAddO /= 0 else
            (others => '0');
    AbsAddO <= AddO(23 downto 0) when AddO(24) = '0' else
	           not(AddO(23 downto 0)) + 1;     
	   
    process(AbsAddO)
        variable TempCarry : std_logic_vector(4 downto 0);
        variable AbsAddOVar: std_logic_vector(23 downto 0);
        constant One : std_logic_vector(1 downto 0) := "01";
    begin
        TempCarry := (others => '0');
        AbsAddOVar := AbsAddO;
        for i in 0 to 23 loop
            if AbsAddO(23 - i) = '0' then
                TempCarry := TempCarry + 1;
                AbsAddOVar := shl(AbsAddOVar,One); 
            else
                exit;
            end if;
        end loop;
        TwoComp <= AbsAddOVar(22 downto 0);
        CarryOut <= TempCarry;
    end process;	   
	   
    process
    begin
        wait until Clk = '1' and Clk'event;
	        DOut(31) <= SignO;
	        DOut(30 downto 23) <= ExpI;
	        DOut(22 downto 0) <= TwoComp;
    end process;
    
end A_Fix2Flt;