v5_1.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;

entity V5_1 is
port(Sel      : in std_logic_vector(1 downto 0);
     OutD     : out std_logic_vector(1 downto 0));
end V5_1;

architecture a of V5_1 is
	
begin
    
    with Sel select
			Outd <= "00" when "00" ,
                    "01" when "01" ,
                    "11" when others;          
    
end a;