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Verilog 的代码
fdwt_all.csf.msg
{ Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "0 0 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.vwf " "Found 0 design units and 0 entities in source file F:\\Program_Back\\Ver
transcript
# Reading D:/Modeltech_pe_edu_6.4a/tcl/vsim/pref.tcl
# OpenFile E:/a-study/course/vhdl-verilog/vhdl/vhdl-project/arbiter/transcript
kit_de2.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_crc is
generic(
tp : integer := 1
);
port(
clk : in vl_logic;
data : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity rcosflt_lookup is
port(
clk : in vl_logic;
nrst : in vl_logic;
din : in vl_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity decoder15 is
port(
clk : in vl_logic;
r : in vl_logic_vector(14 downto 0);
c
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity w is
port(
alu_out : in vl_logic_vector(7 downto 0);
w_ena : in vl_logic;
w_out : out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ir is
port(
instruction : in vl_logic_vector(11 downto 0);
reset : in vl_logic;
clk1 : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity alu is
generic(
ADDWF : integer := 0;
MOVLW : integer := 1;
ANDWF : integer := 2;
CL
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity risc_mcu is
port(
clk : in vl_logic;
reset : in vl_logic;
instruction : in vl_logic_