_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity w is
    port(
        alu_out         : in     vl_logic_vector(7 downto 0);
        w_ena           : in     vl_logic;
        w_out           : out    vl_logic_vector(7 downto 0);
        clk1            : in     vl_logic;
        reset           : in     vl_logic
    );
end w;