_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity ir is
    port(
        instruction     : in     vl_logic_vector(11 downto 0);
        reset           : in     vl_logic;
        clk1            : in     vl_logic;
        ir_jump         : in     vl_logic;
        ir_out          : out    vl_logic_vector(11 downto 0)
    );
end ir;