_primary.vhd

来自「此代码可用modelsim进行仿真」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity risc_mcu is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        instruction     : in     vl_logic_vector(11 downto 0);
        ram_out         : in     vl_logic_vector(7 downto 0);
        fsr_out         : in     vl_logic_vector(7 downto 0);
        pc_addr         : out    vl_logic_vector(10 downto 0);
        clk1            : out    vl_logic;
        clk3            : out    vl_logic;
        alu_out         : out    vl_logic_vector(7 downto 0);
        in_wdrd         : out    vl_logic_vector(7 downto 0);
        w_reg           : out    vl_logic;
        r_reg           : out    vl_logic
    );
end risc_mcu;