_primary.vhd

来自「用verilog编写的bch译码器」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity decoder15 is
    port(
        clk             : in     vl_logic;
        r               : in     vl_logic_vector(14 downto 0);
        c               : out    vl_logic_vector(14 downto 0)
    );
end decoder15;