fdwt_all.csf.msg

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "0 0 F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.vwf " "Found 0 design units and 0 entities in source file F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.vwf" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"Datapath.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"Datapath.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"Datapath.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"Datapath.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"Datapath.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"Datapath.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"Datapath.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"Datapath.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"PctoFPGA.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"PctoFPGA.v\"
" {  } {  }  }
{  Warning "WVLGX_IGNORE_BITRANGE_DECL" "parameter " "Parameter Declaration warning: ignored illegal part-select in parameter Declaration" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 0 0 } }  }  }
{  Warning "WVLGX_IGNORE_BITRANGE_DECL" "parameter " "Parameter Declaration warning: ignored illegal part-select in parameter Declaration" {  } { { "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" "" "" { Text "F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v" 1 0 0 } }  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"PctoFPGA.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"PctoFPGA.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"PctoFPGA.v\"