_primary.vhd

来自「运用FPGA控制AD9957的操作」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity rcosflt_lookup is
    port(
        clk             : in     vl_logic;
        nrst            : in     vl_logic;
        din             : in     vl_logic;
        dout            : out    vl_logic_vector(15 downto 0)
    );
end rcosflt_lookup;