kit_de2.map.qmsg

VGA sourcecodes/documents

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 31 20:20:57 2008 " "Info: Processing started: Sat May 31 20:20:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off kit_DE2 -c kit_DE2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off kit_DE2 -c kit_DE2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO_Image.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIFO_Image.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIFO_Image " "Info: Found entity 1: FIFO_Image" {  } { { "FIFO_Image.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/FIFO_Image.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "asyn_receiver.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file asyn_receiver.v" { { "Info" "ISGN_ENTITY_NAME" "1 async_receiver " "Info: Found entity 1: async_receiver" {  } { { "asyn_receiver.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/asyn_receiver.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control_wr_rd_for_SRAM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file control_wr_rd_for_SRAM.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_wr_rd_for_SRAM " "Info: Found entity 1: control_wr_rd_for_SRAM" {  } { { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Khoi_FIFO.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Khoi_FIFO.v" { { "Info" "ISGN_ENTITY_NAME" "1 Khoi_FIFO " "Info: Found entity 1: Khoi_FIFO" {  } { { "Khoi_FIFO.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Khoi_FIFO.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "kit_DE2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file kit_DE2.v" { { "Info" "ISGN_ENTITY_NAME" "1 kit_DE2 " "Info: Found entity 1: kit_DE2" {  } { { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Processing_image.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Processing_image.v" { { "Info" "ISGN_ENTITY_NAME" "1 Processing_image " "Info: Found entity 1: Processing_image" {  } { { "Processing_image.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Processing_image.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Processing_image_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Processing_image_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 Processing_image_0 " "Info: Found entity 1: Processing_image_0" {  } { { "Processing_image_0.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Processing_image_0.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Processing_image_1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Processing_image_1.v" { { "Info" "ISGN_ENTITY_NAME" "1 Processing_image_1 " "Info: Found entity 1: Processing_image_1" {  } { { "Processing_image_1.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Processing_image_1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram_vga.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram_vga.v" { { "Info" "ISGN_ENTITY_NAME" "1 ram_vga " "Info: Found entity 1: ram_vga" {  } { { "ram_vga.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/ram_vga.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAM_interface.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAM_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAM_interface " "Info: Found entity 1: SRAM_interface" {  } { { "SRAM_interface.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/SRAM_interface.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_controller.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file vga_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_controller " "Info: Found entity 1: vga_controller" {  } { { "vga_controller.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 Khoi_phat_hien_canh_len " "Info: Found entity 2: Khoi_phat_hien_canh_len" {  } { { "vga_controller.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 159 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_sync.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file vga_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_sync " "Info: Found entity 1: vga_sync" {  } { { "vga_sync.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_sync.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 D_FFs " "Info: Found entity 2: D_FFs" {  } { { "vga_sync.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_sync.v" 122 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "kit_DE2 " "Info: Elaborating entity \"kit_DE2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "async_receiver async_receiver:BLOCK1 " "Info: Elaborating entity \"async_receiver\" for hierarchy \"async_receiver:BLOCK1\"" {  } { { "kit_DE2.v" "BLOCK1" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 65 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_controller vga_controller:BLOCK2 " "Info: Elaborating entity \"vga_controller\" for hierarchy \"vga_controller:BLOCK2\"" {  } { { "kit_DE2.v" "BLOCK2" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 87 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram_vga vga_controller:BLOCK2\|ram_vga:VGA_khoi1 " "Info: Elaborating entity \"ram_vga\" for hierarchy \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\"" {  } { { "vga_controller.v" "VGA_khoi1" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 52 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/chuong_trinh/quartusii/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/chuong_trinh/quartusii/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/chuong_trinh/quartusii/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\"" {  } { { "ram_vga.v" "altsyncram_component" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/ram_vga.v" 71 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\"" {  } { { "ram_vga.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/ram_vga.v" 71 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_4qc1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4qc1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_4qc1 " "Info: Found entity 1: altsyncram_4qc1" {  } { { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 40 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_4qc1 vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated " "Info: Elaborating entity \"altsyncram_4qc1\" for hierarchy \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/chuong_trinh/quartusii/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_4oa.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_4oa.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_4oa " "Info: Found entity 1: decode_4oa" {  } { { "db/decode_4oa.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/decode_4oa.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}