sram_interface.v

来自「VGA sourcecodes/documents」· Verilog 代码 · 共 41 行

module	SRAM_interface(
						in_address,
						wr_or_rd,
						in_data,
						//////////// interface cua SRAM ///////////////////
						oSRAM_DQ,
						oSRAM_ADDR,
						oSRAM_UB_N,
						oSRAM_LB_N,
						oSRAM_WE_N,
						oSRAM_CE_N,
						oSRAM_OE_N,
						/////////// data for ram vga //////////////////////
						data_ram_vga
					   );
input	[17:0]in_address;
input	wr_or_rd;
input	[15:0]in_data;
					
inout	[15:0]	oSRAM_DQ;			//	SRAM Data bus 16 Bits
output	[17:0]	oSRAM_ADDR;			//	SRAM Address bus 18 Bits
output			oSRAM_UB_N;			//	SRAM High-byte Data Mask 
output			oSRAM_LB_N;			//	SRAM Low-byte Data Mask 
output			oSRAM_WE_N;			//	SRAM Write Enable
output			oSRAM_CE_N;			//	SRAM Chip Enable
output			oSRAM_OE_N;			//	SRAM Output Enable

output	[15:0]data_ram_vga;

assign oSRAM_UB_N = 0;					// hi byte select enabled
assign oSRAM_LB_N = 0;					// lo byte select enabled
assign oSRAM_CE_N = 0;					// chip is enabled
assign oSRAM_OE_N = ~oSRAM_WE_N;		//output enable is overidden by WE

assign	oSRAM_WE_N = ~wr_or_rd;
assign  oSRAM_DQ = (~wr_or_rd? 16'hzzzz : in_data );
assign	data_ram_vga = oSRAM_DQ;
assign	oSRAM_ADDR = in_address;

endmodule