代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/443994/7619493
vhd bin16_bcd5.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
--Component Bin16_Bcd5
-- PORT ( Clk : IN STD_LOGIC;
-- BinIN : IN std_logic_ve
www.eeworm.com/read/443696/7626955
vhd atahost_dma_actrl.vhd
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller
www.eeworm.com/read/443250/7635414
vhd v6_13.vhd
library ieee;
use ieee.std_logic_1164.all;
entity FIFO is
port(FIFOIn : in std_logic_vector(7 downto 0);
FIFOOut : out std_logic_vector(7 downto 0);
WR : in std_logic
www.eeworm.com/read/443250/7635481
vhd v5_4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity V5_4 is
port(clk : in std_logic;
rst : in std_logic;
dataouts : out std_logic;
d
www.eeworm.com/read/442917/7642362
vhd elec_lock.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library altera;
use altera.maxplus2.all;
entity elec_lock is
port(
clk_4M:in std_
www.eeworm.com/read/442482/7650507
vhd xminute.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xminute is
port (
clkmin: in STD_LOGIC;
reset: in STD_LOGI
www.eeworm.com/read/442482/7650547
vhd xsecond.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xsecond is
port (
clk: in STD_LOGIC;
clkset: in STD_LOGIC;
www.eeworm.com/read/441657/7667615
vhd ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ctrl is
port(cn,res,clk:in std_logic;
cout:out std_logic;
low,high:out std_logic
www.eeworm.com/read/441530/7669156
vhd clk_div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port(clk : in std_logic;
flag1,flag2: out std_logic;
clk_d
www.eeworm.com/read/441204/7674563
txt hdb3.txt
1. +V码检测模块的VHDL程序设计
依据上述建模思想，编写其VHDL程序如下：
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Zv is --+Ｖ码检测器的实体名
port (fb