xminute.vhd

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library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity xminute is
    port (
        clkmin: in STD_LOGIC;
        reset: in STD_LOGIC;
        sethour: in STD_LOGIC;
        clk: in STD_LOGIC;
        minout: out STD_LOGIC_VECTOR (6 downto 0);
        enhour: out STD_LOGIC
    );
end xminute;

architecture xminute_arch of xminute is
signal min : std_logic_vector(6 downto 0);
signal ehour : std_logic;
signal min1 : std_logic;
begin
  -- <<enter your statements here>>

  process(reset,clk,sethour,min,ehour)
  begin
  if reset='0' then
    enhour<='0';
    minout<="0000000";
    min1<='0';
  else
    min1<='1';
    minout<=min;
    if clk='1' and clk'event then
     if sethour='0' then
       enhour<='1';
     else
       enhour<=ehour;
     end if;
    end if;
  end if;
  end process;   

process(clkmin,min1)
  alias lcountm : std_logic_vector(3 downto 0) is min(3 downto 0);
  alias hcountm : std_logic_vector(2 downto 0) is min(6 downto 4);
begin
    if min1='0' then
       min<="0000000";
    else
     if (clkmin='1' and clkmin'event) then           
      if lcountm=9 then
         lcountm<="0000";
         if hcountm/=5 then
          hcountm<=hcountm+1;
          ehour<='0';
         else
          hcountm<="000";
          ehour<='1';
         end if;
      else
         lcountm<=lcountm+1;
         ehour<='0';
      end if;
     end if;
    end if;
end process;

end xminute_arch;