bin16_bcd5.vhd

it is a binary16 to BCD converter .it will work on spartan 3 xilini devices.

LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.all;
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;


--Component Bin16_Bcd5
--	PORT (	Clk				: IN	STD_LOGIC;
--					BinIN 		: IN  std_logic_vector (15 downto 0);
--					BcdOut		: OUT std_logic_vector (19 downto 0) );	
--end component;
--

--pBinBcd: Bin16_Bcd5 port map (Clk    => CLK,
--															BinIN  => sBinIN,
--															BcdOut => sBcdOut );	

-------------------------------------------------------------------
ENTITY Bin16_Bcd5 IS
	PORT
	(
		Clk				: IN	STD_LOGIC;
		BinIN 		: IN  std_logic_vector (15 downto 0);
		BcdOut		: OUT std_logic_vector (19 downto 0)
	);	
END Bin16_Bcd5;


ARCHITECTURE a OF Bin16_Bcd5 is

	 type    TStates is (S0, S1, S2);

	subtype Nibble is std_logic_vector (3 downto 0);
	type  	TBcd is array (0 to 4) of Nibble;
	signal 	sBCD 		: TBcd;
	
begin

pBin16BCD:	process (Clk)
						variable State : TStates;
						variable cnt	  : std_logic_vector (15 downto 0);
						begin
							if rising_edge (Clk) then
								case State is
									when S0 =>	cnt := (others => '0'); 
															for i in 0 to 4 loop
																sBcd(i) <= x"0";	
															end loop;
															State := S1;
									
									when S1 =>	cnt := cnt + 1;
															if (cnt < BinIN) then
																	
																	if (sBcd(0) < 9) then
																		sBcd(0) <= sBcd(0) + 1;
																	else
																		sBcd(0) <= x"0";
																		
																		if (sBcd(1) < 9) then
																			sBcd(1) <= sBcd(1) + 1;
																		else
																			sBcd(1) <= x"0";
																			
																			if (sBcd(2) < 9) then
																				sBcd(2) <= sBcd(2) + 1;
																			else
																				sBcd(2) <= x"0";
																				
																				if (sBcd(3) < 9) then
																					sBcd(3) <= sBcd(3) + 1;
																				else
																					sBcd(3) <= x"0";

																					if (sBcd(4) < 9) then
																						sBcd(4) <= sBcd(4) + 1;
																					else
																						sBcd(4) <= x"0";
																					end if;
																				end if;
																			end if;
																		end if;
																	end if;
															else
																State := S2;
															end if;
															
									when S2 =>  for i in 0 to 4 loop
																BcdOut(i*4+3 downto i*4) <= sBcd(i);
															end loop;
															State := S0;
															
									when others => State := S0;
								end case;
							end if;
						end process;
			
END a;