v5_4.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity V5_4 is
  port(clk	    : in std_logic;
       rst		: in std_logic;
       dataouts : out std_logic;
       dataoutv	: out std_logic);
end V5_4;

architecture a of V5_4 is

		signal temps : std_logic_vector(3 downto 0);

begin
		process(rst,clk)
			variable tempv : std_logic_vector(3 downto 0);
		begin
			if rst = '0' then
				dataoutv <= '0';
				dataouts <= '0';
				tempv := "0000";
				temps <= "0000";
			elsif clk = '1' and clk'event then
				tempv := tempv + 1;
				temps <= temps + 1;
				if tempv > "0011" then
					dataoutv <= '0';
				else
					dataoutv <= '1';
				end if;
				if temps > "0011" then
					dataouts <= '0';
				else
					dataouts <= '1';
				end if;
			end if;
		end process;
end a;