v6_13.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity FIFO is 
	port(FIFOIn	  	: in  std_logic_vector(7 downto 0);
	    FIFOOut  	: out  std_logic_vector(7 downto 0);
	    WR       	: in  std_logic;
	    RD       	: in  std_logic;
	    RS       	: in  std_logic);
end FIFO;

architecture A_FIFO of FIFO is

	type mem is array(0 to 7) of std_logic_vector(7 downto 0);
	signal memroom : mem;
	signal WRPoint : integer range 0 to 7;
	signal RDPoint : integer range 0 to 7;
	
begin
	process(RS,RD)
	begin		
		if RS = '0' then
			RDPoint <= 0;
		elsif RD = '1' and RD'event then
			if RDPoint = 7 then
				RDPoint <= 0;
			else
				RDPoint <= RDPoint + 1;
			end if;	
			FIFOOut <= memroom(RDPoint);		
		end if;
	end process;
	process(RS,WR)
	begin
		if RS = '0' then
			WRPoint <= 0;
			for i in 0 to 7 loop
				for j in 0 to 7 loop
					memroom(i)(j) <= '0';
				end loop;
			end loop;
		elsif WR = '1' and WR'event then
			if WRPoint = 7 then
				WRPoint <= 0;
			else
				WRPoint <= WRPoint + 1;
			end if;	
			memroom(WRPoint) <= FIFOIn;		
		end if;
	end process;
end A_FIFO;