ctrl.vhd

来自「quarters2编写的定时器.vhd为源程序」· VHDL 代码 · 共 50 行

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
     entity ctrl is 
     port(cn,res,clk:in std_logic;
     cout:out std_logic;
     low,high:out std_logic_vector(3 downto 0));
     end ctrl;
     architecture rtl of ctrl is signal
     displow,disphigh:std_logic_vector(3 downto 0);
     begin
     a:process(clk,cn,res)
     variable cnt:integer range 0 to 59;
     begin
     if(res='0')then
     displow<="0000";
     disphigh<="0000";
     cnt:=0;
     cout<='0';
     elsif(clk'event and clk='1')then
     if cn='1' then
     if displow<="1001"then
     displow<=displow+'1';
     else displow<="0000";
     disphigh<=disphigh+'1';
     end if;
     else
     if cnt<59 then
     cnt:=cnt+1;
     else
     cnt:=0;
     if displow>=1 then
     displow<=displow-'1';
     elsif displow=1 then
     displow<="0000";
     if disphigh=0 then
     cout<='1';
     end if;
     elsif(disphigh>0)then
     disphigh<=disphigh-1;
     displow<="1001";
     end if;
     end if;
     end if;
     end if;
     end process;
     high<=disphigh;
     low<=displow;
     end rtl;