xsecond.vhd

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity xsecond is
    port (
        clk: in STD_LOGIC;
        clkset: in STD_LOGIC;
        setmin: in STD_LOGIC;
        reset: in STD_LOGIC;
        secout: out STD_LOGIC_VECTOR (6 downto 0);
        enmin: out STD_LOGIC
    );
end xsecond;

architecture xsecond_arch of xsecond is
signal sec : std_logic_vector(6 downto 0);
signal emin : std_logic;
signal sec1 : std_logic;
begin
  -- <<enter your statements here>>

  process(reset,sec,emin,setmin,clkset)
  begin
  if reset='0' then
    enmin<='0';
    secout<="0000000";
    sec1<='1';
  else
    sec1<='0';
    secout<=sec;
    if clkset='1' and clkset'event then
      if setmin='0' then
         enmin<='1';
      else
         enmin<=emin;         
      end if;
    end if;
  end if;
  end process;   
  
  process(clk,sec1)
  alias lcount : std_logic_vector(3 downto 0) is sec(3 downto 0);
  alias hcount : std_logic_vector(2 downto 0) is sec(6 downto 4);
  begin
    if sec1='1' then
      sec<="0000000";
    else
    if (clk='1' and clk'event) then           
      if lcount=9 then
         lcount<="0000";
         if hcount/=5 then
          hcount<=hcount+1;
          emin<='0';
         else
          hcount<="000";
          emin<='1';
         end if;
      else
         lcount<=lcount+1;
         emin<='0';
      end if;
  end if;
  end if;
end process;
end xsecond_arch;