clk_div.vhd

来自「介绍了各种分频器的设计」· VHDL 代码 · 共 74 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
	port(clk 		:	in std_logic;
		 flag1,flag2:   out std_logic;
		 clk_div5	:	out std_logic);
end clk_div;

ARCHITECTURE a of clk_div IS
	constant ld:std_logic_vector(2 downto 0):="010";
	constant md:std_logic_vector(2 downto 0):="100";
	constant zero:std_logic_vector(2 downto 0):=(others=>'0');
	signal countr:std_logic_vector(2 downto 0);
    signal countf:std_logic_vector(2 downto 0);
	signal levelr:std_logic;
	signal levelf:std_logic;

BEGIN
	process(clk)
	begin
		if clk'event and clk='1' then
			if countr=md then 
				countr<=zero;
			else
				countr<=countr+1;
			end if;
		end if;
	end process;

	process(clk)
	begin 
		if clk'event and clk='0' then 
			if countf=md then
				countf<=zero;
			else
				countf<=countf+1;
			end if;
		end if;
	end process;
  
	process(clk)
	begin
		if clk'event and clk='1' then
			if countr=zero then
				levelr<='1';
			elsif countr=ld then	
				levelr<='0';
			end if;
		end if;
	end process;
	
	process(clk)
	begin
		if clk'event and clk='0' then
			if countf=zero then
				levelf<='1';
			elsif countf=ld then 
				levelf<='0';
			end if;
		end if;
	end process;

	process(levelr,levelf)
	begin
		flag1<=levelr;
		flag2<=levelf;
	clk_div5<=levelr or levelf;
	end process;	
END a;