hdb3.txt

vhdl语言实现的hdb3编解码的功能

1.　+V码检测模块的VHDL程序设计
依据上述建模思想，编写其VHDL程序如下： 
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all;
entity Zv is         --+Ｖ码检测器的实体名
 port (fb,zb: IN std_logic;
       zvout:out std_logic);
end ZV;
architecture bh of ZV is
signal M:std_logic_vector(2 downto 0);
begin 
 process(zb,fb)
    begin 
  if fb='1' then M<="000";
   
  elsif zb'event and zb='1' then
          
        if M<2 then 
          M<=M+1;
 end if;
 end if; 
  end process;
process(fb,M)
begin
if fb='0' then
 if M<2 then
    zvout<='0';  
            else 
              zvout<=zb;
 end if;
else 
 zvout<='0'; 
end if;
end process; 
end bh;

2. -V码检测模块的VHDL程序设计
依据上述建模思想，编写其VHDL程序如下： 
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Fv is          -- -Ｖ码检测器的实体名
 port (fb,zb: IN std_logic;
       Fvout:out std_logic);
end FV;
architecture hh of FV is
signal N:std_logic_vector(2 downto 0);
begin 
 process(zb,fb)
    begin 

 if zb='1' then N<="000";
   
  elsif fb'event and fb='1' then
          
        if N<2 then 
          N<=N+1;
 
end if;
 end if; 
  end process;

process(ZB,N)
begin
if ZB='0' then
 if N<2 then
    fvout<='0';  
            else 
              fvout<=fb;
 end if;
 else 
 fVOUT<='0'; 
end if;
end process; 
end hh;

3.扣Ｖ扣Ｂ模块程序设计
依据扣Ｖ扣Ｂ模块的建模思想，编写其VHDL程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Kvb IS       --扣Ｖ扣Ｂ模块的实体名
  PORT(CLK:IN STD_LOGIC;
       V,datain:IN STD_LOGIC;
      DECODE:OUT STD_LOGIC);
END Kvb;

ARCHITECTURE BEHAV OF Kvb IS
  SIGNAL A0,A1,A2,A3:STD_LOGIC;
 BEGIN
  PROCESS(CLK,v)
   BEGIN
     IF CLK'EVENT AND CLK='1' THEN 
  IF (v='1') THEN
   A0<='0';
       A1<='0';
       A2<='0';
       A3<='0';
   decode <=A0;
  ELSIF (V='0') THEN  
          A3<=DATAIN;
          A2<=A3;
          A1<=A2;
          A0<=A1;
         DECODE<=A0;
 
     END IF;
    END IF;
  END PROCESS;
 END BEHAV; 

4.加法器程序设计
library ieee;
use ieee.std_logic_1164.all;
entity or1 is          --或门的实体名
port(a,b: in std_logic;c: out std_logic);
end entity or1;
architecture one of or1 is
begin
c<=a or b;        --或门逻辑描述
end architecture one;

5. HDB3译码器的元件例化程序设计
library ieee;
use ieee.std_logic_1164.all;
entity DECODE is       --译码器的实体名
port(FB,ZB,CLK: in std_logic;
DECODE,v2,v3: out std_logic);
end entity DECODE;
ARCHITECTURE HH OF DECODE IS
 COMPONENT Kvb                    --kvb
  PORT(CLK:IN STD_LOGIC;
       V,datain:IN STD_LOGIC;
      DECODE:OUT STD_LOGIC       );
END COMPONENT Kvb;
COMPONENT or1               --or1
port(a,b: in std_logic;c: out std_logic);
end component or1;
 
COMPONENT Fv                --fv
 port (fb,zb: IN std_logic;
Fvout:out std_logic);
End component fv;
 
 
Component Zv                 --zv
 port (fb,zb: IN std_logic;
       zvout:out std_logic);
END COMPONENT zv ;
component v1
port(a,b: in std_logic;
     v2,v3:out std_logic);
end component v1;
 
SIGNAL m,x,y,z:std_logic;
begin
  t1: zv port map(fb=>fb,zb=>zb,zvout=>x);
 t2: fv port map(fb=>fb,zb=>zb,fvout=>y);
t3: or1 port map(a=>y,b=>x,c=>z);           -- v相加
t4: or1 port map(a=>fb,b=>zb,c=>m);      -- B相加
t5:kvb port map(clk=>clk,v=>z,datain=>m,decode=>decode);
t6: v1 port map(a=>x,b=>y,v2=>v2,v3=>v3);
end architecture HH; 
library ieee;
 use ieee.std_logic_1164.all;
entity v1 is
port(a,b:in std_logic;
     v2,v3: out std_logic);
end v1;
architecture one of v1 is
  begin
 v2<=a;
v3<=b;
end one;